1. Field of the Invention
This invention relates to an electrostatic protection circuit to prevent damage to a protected circuit due to electrostatic discharge applied to an input/output terminal.
2. Description of the Related Art
In association with reduction in circuit voltages, differences in operating voltage may occur between internal circuits, such as logic circuits, and interface circuits exchanging signals with other circuits. For example, while internal circuits operate on a signal voltage of 1.5V, interface circuits operate on signal voltages of 3.3V and 2.5V. In interface circuits, in order to operate at a signal voltage higher than that of the internal circuit, the thickness of the oxide film on the gates of the Metal Oxide Semiconductor (MOS) transistors provided within the circuits is normally made thicker in the interface circuits than in the internal circuits. A plurality of oxide processes are required to achieve this, and the manufacturing process becomes complex, and costs increase.
On the other hand, electrostatic protection circuits are normally provided to prevent damage to internal circuits due to electrostatic discharge (ESD) occurring in semiconductor integrated circuits when manufacturing LSIs and mounting LSIs on boards. These electrostatic protection circuits are a type of interface circuit, and may operate at a higher signal voltage than the internal circuit.
FIG. 5 shows an example of the configuration of a conventional electrostatic protection circuit. FIG. 5A is an example in which an electrostatic protection circuit is comprised of a single N channel MOS transistor 301. As shown in the figure, the drain of the N channel MOS transistor 301 is connected to the connection point of the input pad (input terminal) 1 and internal circuit 50. The N channel MOS transistor 301 gate and source are both connected to the GND terminal. From the point of view of reliability of the MOS transistor, a signal voltage higher than the operating voltage of the MOS transistor can generally not be input in this electrostatic protection circuit. For example, when the operating voltage of the MOS transistor is 3.3V, and a 5.0V signal is input, a potential difference of 5.0V occurs between the drain and gate of the N channel MOS transistor 301, and the gate oxide film is stressed to a voltage of 5.0V. When the operating voltage of the MOS transistor is 3.3V, the gate oxide film is also compatible with 3.3V, and stressing to a voltage of 5.0V will result in a dramatic loss of reliability.
The electrostatic protection circuit shown in FIG. 5B is therefore generally employed when a signal voltage higher than the operating voltage of the MOS transistor is input. In the electrostatic protection circuit shown in FIG. 5B, the N channel MOS transistors 302 and 303 are connected in cascode configuration. The drain of the N channel MOS transistor 302 is connected to the connection point of the input pad 1 and internal circuit 50, the gate is connected to the power supply terminal (for example, 3.3V power supply), and the source is connected to the drain of the N channel MOS transistor 303. Furthermore, the gate and source of the N channel MOS transistor 303 are both connected to the GND terminal.
In this electrostatic protection circuit, even if the operating voltage of the N channel MOS transistors 302 and 303 is 3.3V, a 5.0V signal input is possible. When a 5.0V signal is input to signal pad 1, the voltage stress applied to the oxide film of the gate of the N channel MOS transistor 302 is 5.0V−3.3V=1.7V. Even when the signal voltage input to the signal pad 1 varies between 0V and 5.0V, the electric potential between the drain and gate of the N channel MOS transistor 302 does not exceed 3.3V. Furthermore, the drain voltage of the N channel MOS transistor 303 is a maximum of 3.3V−Vt (Vt being the threshold voltage of the N channel MOS transistor 302), and the electric potential between the drain and gate of the N channel MOS transistor 303 does not exceed 3.3V. Thus, in the electrostatic protection circuit shown in FIG. 5B, reliability is not lost even if a signal voltage higher than the MOS transistor operating voltage is input.
However, in the circuit shown in FIG. 5B, a problem exists in relation to discharge capacity. This point is described in reference to FIG. 6. FIG. 6A is a cross-sectional diagram showing the structure of the circuit example shown in FIG. 5A. FIG. 6B is a cross-sectional diagram showing the structure of the circuit example shown in FIG. 5B.
When ESD stress is applied to these circuits, current flows to the GND terminal due to NPN bipolar operation. The shorter the distance L between the N+ diffusion layers, therefore, the better the bipolar performance, and the greater the discharge capacity. Since the distance L shown in FIG. 6B is naturally longer that the distance L shown in FIG. 6A for reasons of structure, bipolar performance is low, and discharge capacity is inevitably reduced. In 3.3V transistors using 0.15 μm CMOS technology, for example, the distance L is 0.1 μm or greater. Thus, in the circuit shown in FIG. 5B having the structure shown in FIG. 6B, the dimension W in the depth direction of the page in FIG. 6B must be increased.
However, increasing the dimension W increases the parasitic capacitance C, and results in a loss in clarity of the signal input to the input pad 1, thus introducing a problem in that high-speed operation is prevented. When the distance L in FIG. 6B is equal to or greater than 1.0 μm, parasitic capacitance C becomes 2 pF or greater in order to ensure the prescribed ESD resistance (for example, a resistance of 2000V or greater in tests using the Human Body Model). At this parasitic capacitance, high-speed operation (GHz band) is impossible.
Occurrence of the same problem is noted in the electrostatic protection circuit disclosed in U.S. Pat. No. 5,932,918 and in ‘ESD Protection for Mixed Voltage I/O Using NMOS Transistors Stacked in Cascode Configuration’, Warren R. Anderson and David B. Krakauer, EOS/ESD Symposium 98-54.
As described above, in the conventional electrostatic protection circuit shown in FIG. 5A, there was a problem in that reliability was lost when a signal voltage higher than the operating voltage of the internal circuit was input. Furthermore, as shown in FIG. 5B, there was a problem in the conventional electrostatic protection circuit in that both a high ESD resistance and a low parasitic capacitance compatible with high-speed circuit operation could not be obtained simultaneously.